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Memory barrier
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41	D07 2004 coverW.a1me (Page 1) Add to Reading List Source URL: www.aristeia.com Language: English - Date: 2013-01-31 17:34:58 Software design patterns Concurrency control Cross-platform software Singleton pattern Double-checked locking Memory barrier Volatile variable Lock Singleton Computing Software engineering Computer programming
42	This is the author’s version of the work. The definitive work was published in Proceedings of the 20th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2009), pp Add to Reading List Source URL: www12.informatik.uni-erlangen.de Language: English - Date: 2009-07-28 09:29:41 Parallel computing GPGPU Graphics hardware Video cards Cell Lookup table Memory barrier Multi-core processor Compiler optimization Computing Computer hardware Computer architecture
43	This is the author’s version of the work. The definitive work was published in Proceedings of the 9th International Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS Workshop), pp, 2009. Effi Add to Reading List Source URL: www12.informatik.uni-erlangen.de Language: English - Date: 2009-07-28 09:48:50 GPGPU Graphics hardware Concurrent computing Video cards Nvidia Thread CUDA Kernel Memory barrier Computing Computer architecture Computer hardware
44	Thread Synchronization Policies in DrJava Since DrJava is built using the Java Swing library, it must conform to the synchronization policies for Swing. Unfortunately, the official Swing documentation is sparse and misl Add to Reading List Source URL: www.cs.rice.edu Language: English - Date: 2010-01-25 17:20:25 Java programming language Java platform Computer memory Concurrency Lock Thread Memory barrier Java Memory Model Memory model Computing Software engineering Concurrency control
45	Thread Synchronization Policies in DrJava Since DrJava is built using the Java Swing library, it must conform to the synchronization policies for Swing. Unfortunately, the official Swing documentation is sparse and misle Add to Reading List Source URL: www.cs.rice.edu Language: English - Date: 2010-01-25 17:20:25 Java programming language Java platform Computer memory Concurrency Lock Thread Memory barrier Java Memory Model Memory model Computing Software engineering Concurrency control
46	This is the author’s version of the work. The definitive work was published in Transactions on High-Performance Embedded Architectures and Compilers (Transactions on HiPEAC), 2011. Efficient Mapping of Streaming Applic Add to Reading List Source URL: www12.informatik.uni-erlangen.de Language: English - Date: 2011-01-13 06:59:48 GPGPU Graphics hardware Parallel computing Video cards CUDA Thread OpenCL Memory barrier Kernel Computing Computer hardware Concurrent computing
47	This is the author’s version of the work. The definitive work was published in Proceedings of the SPIE: Medical Imaging 2011: Image Processing, Lake Buena Vista, Orlando, FL, USA, February 12-17, 2011. Detector Defect Add to Reading List Source URL: www12.informatik.uni-erlangen.de Language: English - Date: 2011-01-15 11:56:21 Video cards Nvidia Parallel computing GPGPU CUDA Thread Nvidia Quadro Memory barrier Multi-core processor Computing Concurrent computing Computer hardware
48	OMPC++ \| A Portable High-Performance Implementation of DSM using OpenC++ Re ection Yukihiko Sohda, Hirotaka Ogawa, and Satoshi Matsuoka Department of Mathematical and Computing Sciences Tokyo Institute of Technology Add to Reading List Source URL: www.openjit.org Language: English Cross-platform software OpenC++ OpenMP Distributed shared memory Metaclass C Initialization Parallel programming model Memory barrier Computing Software engineering Computer programming
49	OpenMP and the Gaussian Quantum Chemistry Package: Experiences, Limitations and Future Prospects Alistair Rendell Department of Computer Science Add to Reading List Source URL: www.compunity.org Language: English - Date: 2007-10-15 03:40:53 OpenMP Thread Gaussian Barrier C dynamic memory allocation Computing Parallel computing Computer programming
50	Point-to-Point Synchronisation on Shared Memory Architectures J. Mark Bull and Carwyn Ball EPCC, The King’s Buildings, The University of Edinburgh, Mayfield Road, Edinburgh EH9 3JZ, Scotland, U.K. email: Add to Reading List Source URL: www.compunity.org Language: English - Date: 2007-10-15 03:40:58 Computer programming OpenMP Barrier Thread Scheduling CPU cache Computing Concurrent computing Parallel computing

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